Semiconductor integrated circuit device, and method of manufacturing the same

ABSTRACT

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta 2 O 5  (tantalum oxide) film  46,  the portions of bit lines BL and first-layer interconnect lines  23  to  26  of a peripheral circuit which are in contact with at least an underlying silicon oxide film  28  are formed of a W film, the bit lines BL and the interconnect lines  23  to  26  being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines  23  to  26  and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice and the art of manufacturing the same; and, more specifically,the invention relates to improvements applicable to a semiconductorintegrated circuit device having a DRAM (Dynamic Random Access Memory).

The memory cells of a DRAM are arranged at the cross points of aplurality of word lines and a plurality of bit lines all, of which arearranged in the form of a matrix over the principal surface of asemiconductor substrate, and each of the memory cells includes onememory cell selecting MISFET and one information storing capacitiveelement (capacitor) which is connected in series with the memory cellselecting MISFET. The memory cell selecting MISFET mainly includes agate oxide film, a gate electrode formed integrally with a word line,and a pair of semiconductor regions which constitute a source and adrain. The bit line is arranged above the memory cell selecting MISFET,and is electrically connected to either one of the source and the drain.The information storing capacitive element is similarly arranged abovethe memory cell selecting MISFET, and is electrically connected to theother of the source and the drain.

As is known, recent types of DRAMs have adopted a so-called stackedcapacitor structure in which information storing capacitive elements arearranged above memory cell selecting MISFETs to compensate for adecrease in the charge storage quantity per information storingcapacitive element due to the scaling of memory cells. DRAMs which adoptthis stacked capacitor structure are divided into two kinds, a capacitorunder bitline (CUB) structure in which information storing capacitiveelements are arranged below bit lines and a capacitor over bitline (COB)structure in which information storing capacitive elements are arrangedabove bit lines.

In the above-described two kinds of stacked capacitor structures, ascompared with the CUB structure, the COB structure in which informationstoring capacitive elements are arranged above bit lines is suited tothe scaling of memory cells. This is because, if the charge storagequantity of a scaled information storing capacitive element is to beincreased, it is necessary to three-dimensionally design the structureof the information storing capacitive element and increase the surfacearea thereof, but in the case of the CUB structure in which bit linesare arranged above information storing capacitive elements, contactholes for connecting the bit lines and the memory cell selecting MISFETsbecome extremely large in aspect ratio and the contact holes becomedifficult to open.

In the case of recent large-capacity DRAMs such as 64- or 256-MbitDRAMs, it has become difficult to ensure the required charge storagequantity merely by three-dimensionally forming information storingcapacitive elements and increasing the surface areas thereof, and inaddition to the three-dimensional formation of the capacitive elements,consideration has been given to the use of a capacitive insulating filmformed of a high dielectric material such as Ta₂O₅ (tantalum oxide),(Ba, Sr)TiO₃ (barium strontium titanate; hereinafter referred to as BST)or SrTiO₃ (strontium titanate; hereinafter referred to as STO). DRAMsusing a capacitive insulating film formed of such a high dielectricmaterial are described in, for example, Japanese Patent Laid-Open No.222469/1989 and U.S. Pat. No. 5,383,088.

Furthermore, in the field of the above-noted 64-to-256-Mbit DRAMs, ithas been considered inevitable to use a metal material which is lower inresistance than a polycrystalline silicon film, for the material of wordlines and bit lines as a countermeasure for signal delay due to anincrease in chip size, or to use the silicidation technique of forming ahigh melting-point metal silicide layer such as TiSi₂ (titaniumsilicide) or CoSi₂ (cobalt silicide) over the surfaces of the sourcesand drains of MISFETs which constitute peripheral circuits, such assense amplifiers and word drivers, which are required to performhigh-speed operation, as a countermeasure for avoiding an increase inresistance due to the scaling of contact holes for connectinginterconnect lines and the sources and drains of the MISFETs. Thissilicidation technique is described in, for example, Japanese PatentLaid-Open Nos. 29240/1994 and 181212/1996.

SUMMARY OF THE INVENTION

In DRAMs which belong to a 256-Mbit or later generation, as acountermeasure for signal delay due to an increase in chip size, thegate electrodes (word lines) of memory cell selecting MISFETs and thegate electrodes of MISFETs of peripheral circuits are formed of alow-resistance material mainly made of a high melting-point metal suchas W (tungsten), and as a countermeasure for decreasing the contactresistance between diffusion layers and interconnect lines, a highmelting-point silicide layer is formed over the surfaces of the sourcesand drains of the MISFETs which constitute the peripheral circuits.

In such DRAMs, as a countermeasure for the signal delay of bit lines,the bit lines are formed of a low-resistance material mainly made of ahigh melting-point metal such as W, and as a countermeasure for reducingthe number of process steps for forming the interconnect lines, the bitlines and first-layer interconnect lines of the peripheral circuits areformed at the same time in one process step. Moreover, in the DRAMs, asa countermeasure for ensuring the charge storage quantities of theinformation storing capacitive elements, a COB structure in whichinformation storing capacitive elements are arranged above a bit line isadopted to facilitate the three-dimensional formation of the capacitiveelements, and capacitive insulating films are formed of a highdielectric material such as Ta₂O₅ (tantalum oxide).

However, the present inventor has examined the above-described DRAMmanufacturing process and has discussed a phenomenon in which the bitlines formed above the MISFETs and the first-layer interconnect lines ofthe peripheral circuits have peeled off the surfaces of the insulatingfilms during high-temperature heat treatment which was performed in asubsequent process step for forming the information storing capacitiveelements.

The outline of a process for manufacturing the above-described type ofDRAM will be described in brief below. First of all, a low-resistancematerial which is mainly made of a high melting-point metal depositedover a principal surface of a semiconductor substrate is patterned toform gate electrodes (word lines) of memory cell selecting MISFETs andgate electrodes of MISFETs of a peripheral circuit, and then an impurityis ion-implanted into the semiconductor substrate to form the sourcesand drains of these MISFETs.

Then, after these MISFETs are covered with an insulating film, contactholes are formed in the insulating film above the respective sources anddrains of the memory cell selecting MISFETs, and polycrystalline siliconplugs are buried into the respective contact holes. Then, after contactholes are formed in the insulating film above the respective gateelectrodes, sources and drains of the MISFETs of the peripheral circuit,a high melting-point metal film such as a Ti film or a Co film is thinlydeposited over the insulating film as well as the interiors of thesecontact holes. Then, the semiconductor substrate is heat-treated tocause the substrate (Si) and the high melting-point metal to react witheach other at the bottoms of the contact holes, thereby forming a highmelting-point metal silicide layer at the bottoms of the contact holes.

Then, after an interconnect-line material which mainly contains a highmelting-point metal such as W is deposited over the insulating film aswell as the interiors of the contact holes of the peripheral circuit,the interconnect-line material and an unreacted Ti film remaining on thesurface of the insulating film are patterned to form bit lines andfirst-layer interconnect lines of the peripheral circuit over theinsulating film. The bit lines are electrically connected to either thesources or the drains of the memory cell selecting MISFETs through thecontact holes in which the polycrystalline silicon plugs are buried. Thefirst-layer interconnect lines of the peripheral circuit areelectrically connected to any of the gate electrodes, sources and drainsof the MISFETs of the peripheral circuit through the contact holes ofthe peripheral circuit.

Then, the bit lines and the first-layer interconnect lines of theperipheral circuit are covered with an interlayer insulating film, andthrough holes for connecting the sources or the drains of the memorycell selecting MISFETs and information storing capacitive elements areformed in the interlayer insulating film. After that, a conducting filmsuch as polycrystalline silicon which is deposited above thethrough-holes is patterned to form lower electrodes for the informationstoring capacitive elements each having a three-dimensional structure.

Then, after a high dielectric material such as Ta₂O₅ (tantalum oxide) isdeposited over the surfaces of the lower electrodes, high-temperatureheat treatment is performed. Any high dielectric material made of ametal oxide such as Ta₂O₅, BST or STO has a common nature which needshigh-temperature heat treatment of approximately 800° C. after filmformation in order to reduce leakage current. In addition, it isnecessary to take care not to expose the degradation of the film qualityto a high temperature of not less than approximately 450° C., after suchhigh-temperature heat treatment is performed.

Then, after a conducting film such as a TiN film is deposited over thehigh dielectric film, this conducting film and the underlying highdielectric material are patterned to form upper electrodes of theinformation storing capacitive elements and a capacitive insulatingfilm.

However, the present inventor has examined the above-described DRAMmanufacturing process and has discovered a phenomenon in which the bitlines and the first-layer interconnect lines of the peripheral circuithave peeled off the surface of the insulating film during thehigh-temperature heat treatment for improving the film quality of theTa₂O₅ film. This is because, if the Ti film used to form the Ti silicidelayer at the bottoms of the contact holes remains on the insulating filmformed of silicon oxide, peeling occurs at the interface between the Tifilm and silicon oxide, and the reason for this is considered to be thatTi easily forms an oxide compared to Si.

As a countermeasure for preventing the peeling of the Ti film and thesilicon oxide film due to high-temperature heat treatment, there is amethod using an acid etchant to remove an unreacted Ti film whichremains on the surface of the insulating film after the Ti film isheat-treated to form the Ti silicide layer at the bottoms of the contactholes. However, in the process step of forming the contact holes in theinsulating film above the sources and drains of the MISFETs of theperipheral circuit, since contact holes are also formed above the gateelectrodes of the MISFETs at the same time, if the unreacted Ti film isremoved by the etchant after the formation of the Ti silicide film, theetchant also enters the contact holes formed above the gate electrodesand the metal film which constitutes the gate electrodes is etched.Accordingly, the above-described countermeasure is useful in a casewhere the gate electrodes are formed of a polycrystalline silicon filmor a polycide film (a stacked layer made of polycrystalline silicon andhigh melting-point metal silicide) which has resistance to acidetchants, but cannot be applied to a case where the gate electrodes areformed of a material which mainly contains metal.

As a countermeasure for preventing peeling from occurring at theinterface between the Ti film and the silicon oxide film, there is amethod of replacing the Ti film with a TiN (titanium nitride) filmhaving good adhesion to the silicon oxide film by performing heattreatment in a nitrogen atmosphere after a Ti silicide layer is formedby heat-treating the Ti film (or while the Ti silicide is being formed).However, it is difficult to completely replace the Ti film on thesilicon oxide film with the TiN film by heat treatment in a nitrogenatmosphere, so that although the surface of the film may be nitrified,the interface between the film and the silicon oxide film is notcompletely nitrified. In addition, if this high-temperature heattreatment is continued for a long time, the diffusion of impuritiesimplanted in the sources and drains of the MISFETs is promoted to hinderformation of shallow junctions.

An object of the present invention is to provide a way art of preventinga failure in which an underlying interconnect line peels off the surfaceof an insulating film during high-temperature heat treatment to beperformed for improving the film quality of a high dielectric materialin a DRAM in which the capacitive insulating film of an informationstoring capacitive element is formed of the high dielectric material.

The above and other objects and novel features of the present inventionwill become apparent from the following description taken in conjunctionwith the accompanying drawings.

Representative aspects of the invention disclosed herein will bedescribed below in brief.

(1) In a semiconductor integrated circuit device according to thepresent invention, an interconnect line which extends with at least aportion of the interconnect line that is in contact with a siliconoxide-based first insulating film is formed over the first insulatingfilm which is formed over a principal surface of a semiconductorsubstrate, and a capacitive element having a capacitive insulating filmat least a portion of which is formed of a high dielectric film isformed over a second insulating film formed over the interconnect line,and a portion of a conducting film which constitutes the interconnectline, which portion is in contact with the first insulating film overthe first insulating film, is formed of a high melting-point metalexcluding titanium or a nitride of a high melting-point metal.

(2) A semiconductor integrated circuit device according to the presentinvention, comprises a DRAM in which a memory cell selecting MISFETprovided with a gate electrode formed integrally with a word line isformed in a first area over a principal surface of a semiconductorsubstrate, a bit line is formed over a silicon oxide-based firstinsulating film which covers the memory cell selecting MISFET, the bitline being electrically connected to either one of a source and a drainof the memory cell selecting MISFET and extending in contact with thefirst insulating film, and an information storing capacitive element isformed over a second insulating film that is formed over the bit line,the information storing capacitive element being electrically connectedto the other of the source and drain of the memory cell selecting MISFETand having a capacitive insulating film at least a portion of which isformed of a high dielectric film, wherein a portion of a conducting filmwhich constitutes the bit line, which portion is in contact with thefirst insulating film over the first insulating film, is formed of ahigh melting-point metal excluding titanium or a nitride of a highmelting-point metal.

(3) In the semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (2), the highdielectric film is a tantalum oxide film which is subjected to heattreatment for crystallization.

(4) In the semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (2), a conductingfilm which constitutes a gate electrode of the memory cell selectingMISFET is at least partly formed of a metal film.

(5) In the semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (2), a MISFET of aperipheral circuit of the DRAM is formed in a second area over theprincipal area of the semiconductor substrate, a first-layerinterconnect line is formed over the silicon oxide-based firstinsulating film which covers the MISFET of the peripheral circuit, thefirst-layer interconnect line being electrically connected to any one ofa gate electrode, a source and a drain of the MISFET of the peripheralcircuit and extending in contact with the first insulating film, and aportion of a conducting film which constitutes the first-layerinterconnect line, which portion is in contact with the first insulatingfilm over the first insulating film, is formed of a high melting-pointmetal excluding titanium or a nitride of a high melting-point metal.

(6) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), a titaniumsilicide layer is formed at a bottom of a contact hole which is openedin the first insulating film and electrically connects the first-layerinterconnect line and the source or drain of the MISFET of theperipheral circuit.

(7) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), each of theconducting films which respectively constitute the bit line and thefirst-layer interconnect line is a tungsten film.

(8) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), thefirst-layer interconnect line is electrically connected to the source ordrain of the MISFET of the peripheral circuit via a plug which is formedin the contact hole and is formed of a stacked film made of a titaniumfilm and a barrier metal film or a stacked film made of a titanium film,a barrier metal film and a tungsten film.

(9) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), the gateelectrode of the MISFET of the peripheral circuit is formed of a metalfilm.

(10) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), the firstinsulating film is a spin-on-glass film or a silicon oxide filmdeposited by a CVD method.

(11) In a semiconductor integrated circuit device according to thepresent invention as described in the above paragraph (5), asecond-layer interconnect line which is electrically connected to thefirst insulating film is formed over a silicon oxide-based thirdinsulating film formed over the information storing capacitive element,and a portion of a conducting film which constitutes the second-layerinterconnect line is a titanium film, the portion being in contact withthe first insulating film

(12) A method of manufacturing a semiconductor integrated circuitdevice, comprises the steps:

(a) forming a silicon oxide-based first insulating film over a principalsurface of a semiconductor substrate and then depositing a conductingfilm, a portion of which is in contact with the first insulating film,over the first insulating film, the portion being made of a highmelting-point metal excluding titanium or a nitride of a highmelting-point metal including titanium;

(b) patterning the conducting film to form an interconnect line whichextends with at least a portion of the interconnect line that is incontact with the first insulating film, and then forming a secondinsulating film over the interconnect line; and

(c) forming a capacitive element made of a first electrode, a dielectricfilm and a second electrode, over the second insulating film,

the capacitive-element forming step including heat treatment forimproving the film quality of the dielectric film.

(13) A method of manufacturing a semiconductor integrated circuitdevice, comprises the step of:

(a) forming a memory cell selecting MISFET which constitutes a memorycell of a DRAM, in a first area over a principal surface of asemiconductor substrate, and forming a MISFET which constitutes aperipheral circuit of the DRAM, in a second area over the principalsurface of the semiconductor substrate;

(b) forming a silicon oxide-based first insulating film over each of thememory cell selecting MISFET and the MISFET of the peripheral circuit;

(c) forming a first contact hole in the first insulating film over atleast one of a source and a drain of the memory cell selecting MISFET,forming second contact holes in the first insulating film over therespective source and drain of the MISFET of the peripheral circuit, andforming a third contact hole in the first insulating film over a gateelectrode of the MISFET of the peripheral circuit;

(d) depositing a titanium film over the first insulating film as on thewell as interiors of the respective second and third contact holes, andforming titanium silicide layers over surfaces of a source and a drainof the MISFET of the peripheral circuit which are respectively exposedat the bottoms of the second contact holes, by heat-treating thesemiconductor substrate;

(e) depositing a barrier metal film or a stacked film made of thebarrier metal and a high melting-point metal film excluding titaniumover the titanium film as on the well as interiors of the second andthird contact holes and then forming plugs in the respective second andthird contact holes by removing the barrier metal film or the stackedfilm over the first insulating film together with the titanium film;

(f) depositing a conducting film over the first insulating film, atleast a portion of the conducting film which is in contact with thefirst insulating film being made of a high melting-point metal excludingtitanium or a nitride of a high melting-point metal;

(g) patterning the conducting film to form a bit line to be electricallyconnected to one of the source and the drain of the memory cellselecting MISFET through the first contact hole, and forming afirst-layer interconnect line of the peripheral circuit to beelectrically connected to the MISFET of the peripheral circuit throughthe second contact holes or the third contact holes; and

(h) forming an information storing capacitive element made of a firstelectrode, a high dielectric film and a second electrode, over thesecond insulating film,

the capacitive-element forming step including heat treatment forimproving the film quality of the dielectric film.

(14) In a method of manufacturing a semiconductor integrated circuitdevice according to the present invention as described in the aboveparagraph (13), a conducting film which constitutes a gate electrode ofthe memory cell selecting MISFET and a gate electrode of the MISFET ofthe peripheral circuit is a stacked film made of a low-resistancepolycrystalline silicon film doped with an impurity, a barrier metalfilm and a tungsten film.

(15) In a method of manufacturing a semiconductor integrated circuitdevice according to the present invention as described in the aboveparagraph (13), the bit line and the first-layer interconnect line ofthe peripheral circuit are made of a tungsten film.

(16) In a method of manufacturing a semiconductor integrated circuitdevice according to the present invention as described in the aboveparagraph (13), the dielectric film is made of a metal oxide.

(17) In a method of manufacturing a semiconductor integrated circuitdevice according to the present invention as described in the aboveparagraph (16), the metal oxide is tantalum oxide.

(18) In a method of manufacturing a semiconductor integrated circuitdevice according to the present invention as described in the aboveparagraph (13), the heat treatment temperature for improving the filmquality of the dielectric film is 750° C. or more.

(19) A method of manufacturing a semiconductor integrated circuitdevice, comprises the steps of:

(a) forming a memory cell selecting MISFET which constitutes a memorycell of a DRAM, in a first area over a principal surface of asemiconductor substrate, and forming a MISFET which constitutes aperipheral circuit of the DRAM, in a second area over the principalsurface of the semiconductor substrate;

(b) forming a silicon oxide-based first insulating film over each of thememory cell selecting MISFET and the MISFET of the peripheral circuit;

(c) forming a first contact hole in the first insulating film over atleast one of a source and a drain of the memory cell selecting MISFET,forming second contact holes in the first insulating film over therespective source and drain of the MISFET of the peripheral circuit, andforming a third contact hole in the first insulating film over a gateelectrode of the MISFET of the peripheral circuit;

(d) depositing a cobalt film over the first insulating film as well ason the interiors of the respective second and third contact holes, andforming cobalt silicide layers over surfaces of a source and a drain ofthe MISFET of the peripheral circuit which are respectively exposed atbottoms of the second contact holes, by heat-treating the semiconductorsubstrate;

(e) depositing a barrier metal film or a stacked film made of thebarrier metal and a high melting-point metal film excluding cobalt overthe cobalt film as well as on the interiors of the second and thirdcontact holes and then forming plugs in the respective second and thirdcontact holes by removing the barrier metal film or the stacked filmover the first insulating film together with the cobalt film;

(f) depositing a conducting film over the first insulating film, atleast a portion of the conducting film which is in contact with thefirst insulating film being made of a high melting-point metal excludingcobalt or a nitride of a high melting-point metal;

(g) patterning the conducting film to form a bit line to be electricallyconnected to one of the source and the drain of the memory cellselecting MISFET through the first contact hole, and forming afirst-layer interconnect line of the peripheral circuit to beelectrically connected to the MISFET of the peripheral circuit throughthe second contact holes or the third contact holes; and

(h) forming an information storing capacitive element made of a firstelectrode, a high dielectric film and a second electrode, over thesecond insulating film,

the capacitive-element forming step including heat treatment forimproving the film quality of the dielectric film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an entire semiconductor chip over which a DRAMaccording to one embodiment of the present invention is formed;

FIG. 2 is a circuit diagram of the equivalent circuit of the DRAMaccording to the embodiment of the present invention;

FIG. 3 is a cross-sectional view of a representative portion of asemiconductor substrate, partly showing a memory array and a peripheralcircuit of the DRAM according to the embodiment of the presentinvention;

FIG. 4 is a schematic plan view of the semiconductor substrate, partlyshowing the memory array; and

FIGS. 5 to 38 are cross-sectional views of a representative portion of asemiconductor substrate, showing the steps of a method of manufacturingthe DRAM according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described belowin detail with reference to the accompanying drawings. Throughout allthe drawings that illustrate the preferred embodiment, identicalreference numerals are used to denote constituent elements havingidentical functions, and repetition of the same description is omittedfor the sake of simplicity.

FIG. 1 is a plan view of an entire semiconductor chip over which a DRAMaccording to the preferred embodiment is formed. As shown, amultiplicity of memory arrays MARY are arranged in the form of a matrixin the X-direction (along the longer sides of a semiconductor chip 1A)and in the Y-direction (along the shorter sides of the semiconductorchip 1A) over a principal surface of the semiconductor chip 1A made ofsingle-crystal silicon. A sense amplifier SA is arranged between each ofthe memory arrays MARY and adjacent one in the X-direction. Controlcircuits such as word drivers WD and data line selecting circuits,input/output circuits, bonding pads and the like are arranged in thecentral portion of the principal surface of the semiconductor chip 1A.

FIG. 2 is a circuit diagram of the equivalent circuit of theabove-described DRAM. As shown, the memory arrays (MARY) of this DRAMinclude a plurality of word lines WL (WLn−1, WLn, WLn⁺1, . . . ) whichextend in the row direction, a plurality of bit lines BL which extend inthe column direction, and a plurality of memory cells (MC) which arearranged at the cross points of the word lines WL and the bit lines BL.One memory cell for storing one bit of information includes oneinformation storing capacitive element C and one memory cell selectingMISFET Qs which is connected in series with the information storingcapacitive element C. Either one of the source and drain of the memorycell selecting MISFET Qs is electrically connected to the informationstoring capacitive element C, while the other is electrically connectedto the corresponding one of the bit lines BL. One end of each of theword lines WL is connected to the corresponding one of the word driversWD, and one end of each of the bit lines BL is connected to thecorresponding one of the sense amplifiers SA.

FIG. 3 is a cross-sectional view of an essential portion of asemiconductor substrate, partly showing a memory array and a peripheralcircuit of the DRAM, and FIG. 4 is a schematic plan view of thesemiconductor substrate, partly showing the memory array. In FIG. 4,only conducting layers (excluding plate electrodes) which constitutememory cells are shown, but the illustration of interconnect lines whichare formed above the insulating films between the conducting layers orthe memory cells is omitted for clarity.

As shown in FIG. 3, the memory cells of the DRAM are formed in a p-well2 which is formed in the principal surface of a semiconductor substrate1 made of p-type single-crystal silicon. In a region (memory array) inwhich the memory cells are formed, the p-well 2 is electrically isolatedfrom the semiconductor substrate 1 by an n-type semiconductor region 3which is formed below the p-well 2, so that noise is prevented fromentering the p-well 2 from an input/output circuit formed in anotherregion of the semiconductor substrate 1.

Each of the memory cells has a stacked structure in which an informationstoring capacitive element C is arranged above the memory cell selectingMISFET Qs. The memory cell selecting MISFET Qs has an n-channel typestructure, and as shown in FIG. 4, a plurality of memory cell selectingMISFETs Qs are formed in each active region L which is arranged in anelongate island-shaped pattern extending straightforwardly in theX-direction (column direction). In the active region L, two memory cellselecting MISFETs Qs which share either one of a source and a drain(n-type semiconductor regions 9) are formed adjacently to each other inthe X-direction.

Isolation regions which surround the active region L are formed byisolation trenches 6 formed in the p-well 2. A silicon oxide film 5 isburied in the isolation trenches 6, and the surface of the silicon oxidefilm 5 is flattened so as to be approximately equal in height to thesurface of the active region L. The isolation region which is formed bysuch isolation trench 6 has a large effective area compared to anisolation region (field oxide film) formed with the same dimensions by aLOCOS (localized oxidation) process, because no bird's beaks occur atthe edges of the active region L.

The memory cell selecting MISFET Qs mainly includes a gate oxide film 7,a gate electrode 8A, and a pair of n-type semiconductor regions 9 whichconstitute the source and the drain of the memory cell selecting MISFETQs. The gate electrodes 8A of the respective memory cell selectingMISFETs Qs are formed integrally with the word lines WL, and extendstraightforwardly in the Y-direction with the same width and space. Thewidth of each of the gate electrodes 8A, i.e., a gate length, and thespace between two adjacent ones of the gate electrodes 8A (the wordlines WL) are approximately equal to the minimum process dimensionsdetermined by the resolution limit of photolithography. Each of the gateelectrodes 8A (the word lines WL) has a poly-metal structure whichincludes a low-resistance polycrystalline silicon film doped with ann-type impurity such as P (phosphorous), a barrier metal layer formed ofa WN (tungsten nitride) film over the polycrystalline silicon film, anda high melting-point metal film formed of a W (tungsten) film or thelike over the barrier metal layer. The gate electrode 8A (the word lineWL) having the poly-metal structure is low in electrical resistancecompared to a gate electrode formed of a polycrystalline silicon film ora polycide film, so that the signal delay of word lines can be reduced.

The peripheral circuit of the DRAM includes an n-channel type MISFET Qnand a p-channel type MISFET Qp. The n-channel type MISFET Qn is formedin the p-well 2, and mainly includes the gate oxide film 7, a gateelectrode 8B, and a pair of n⁺-type semiconductor regions 10 whichconstitute the source and the drain of the p-channel type MISFET Qp. Thep-channel type MISFET Qp is formed in a p-well 4, and mainly includesthe gate oxide film 7, a gate electrode 8C, and a pair of p⁺-typesemiconductor regions 11 which constitute the source and the drain ofthe p-channel type MISFET Qp. The gate electrodes 8B and 8C havepoly-metal structures identical to those of the gate electrodes 8A (theword lines WL). The n-channel type MISFET Qn and the p-channel typeMISFET Qp which constitute the peripheral circuit are fabricatedaccording to milder design rules than those for memory cells.

A silicon nitride film 12 is formed above the gate electrodes 8A (theword lines WL) of the memory cell selecting MISFETs Qs, and a siliconnitride film 13 is formed over the top and the sidewalls of the siliconnitride film 12 and over the sidewalls of the gate electrodes 8A (theword lines WL). The silicon nitride film 12 is also formed over the topof each of the gate electrodes 8B and 8C of the peripheral circuit, andsidewall spacers 13 s formed of the silicon nitride film 13 are formedover the sidewalls of each of the gate electrodes 8B and 8C.

As will be described later, the silicon nitride film 12 and the siliconnitride film 13 of the memory arrays are used as an etching stopper whencontact holes are being formed by self-alignment above the sources anddrains of the memory cell selecting MISFETs Qs (the n-type semiconductorregions 9). The sidewall spacers 13 s of the peripheral circuit are usedfor giving LDD (Lightly Doped Drain) structures to the source and drainof the n-channel type MISFET Qn and to the source and drain of thep-channel type MISFET Qp LDD.

A SOG film 16 is formed over the top of each of the memory cellselecting MISFETs Qs, the n-channel type MISFET Qn and the p-channeltype MISFET Qp. Silicon oxide films 17 and 18 which constitute twolayers are formed over the SOG film 16, and the surface of the overlyingsilicon oxide film 18 is flattened so as to be approximately equal inheight over the entire area of the semiconductor substrate 1.

Contact holes 19 and 20 are formed to extend through the silicon oxidefilms 18 and 17 as well as the SOG film 16 above the pair of n-typesemiconductor regions 9 which respectively constitute the source and thedrain of each of the memory cell selecting MISFETs Qs. Plugs 21 each ofwhich is formed of a low-resistance polycrystalline silicon film dopedwith an n-type impurity (for example, P (phosphorous)) are buried in therespective contact holes 19 and 20.

The diameter in the X-direction of the bottom of each of the contactholes 19 and 20 is defined by the space between the silicon nitride film13 on a sidewall of one of two opposed gate electrodes 8A (word linesWL) and the silicon nitride film 13 on the opposite sidewall of theother. In other words, each of the contact holes 19 and 20 is formed byself-alignment with respect to the space between two adjacent gateelectrodes 8A (word lines WL).

The diameter in the Y-direction of the contact hole 20 for connection toan information storing capacitive element C is smaller than thedimension of the active region L in the Y-direction. In contrast, thediameter in the Y-direction of the contact hole 19 for connection to thebit line BL (a contact hole above the n-type semiconductor region 9shared by the two memory cell selecting MISFETs Qs) is larger than thedimension of the active region L in the Y-direction. Specifically, thecontact hole 19 is formed in an approximately rectangular plan-viewpattern in which its diameter in the Y-direction is larger than itsdiameter in the X-direction (at its top end), and a portion of thecontact hole 19 extends from the active region L into an area above theisolation trench 6. Since the contact hole 19 is formed in such apattern, it is not necessary to partly increase the width of the bitline BL and extend the bit line BL into an area above the active regionL nor to partly extend the active region L in the direction of the bitline BL, when the bit line BL is to be connected to the n-typesemiconductor region 9 via the contact hole 19. Accordingly, it ispossible to reduce the memory cell size.

A silicon oxide film 28 is formed over the silicon oxide film 18. Athrough-hole 22 is formed in the silicon oxide film 28 above the contacthole 19, and a plug 35 formed of a conducting film in which a Ti film, aTiN film and a W film are stacked in that order from the bottom layer isburied in the through-hole 22. A TiSi₂ (titanium silicide) layer 37,which is produced by the reaction between the Ti film which constitutespart of the plug 35 and a polycrystalline silicon film which constitutesa plug 21, is formed at the interface between the plug 35 and the plug21 buried in the contact hole 19 below the through-hole 22. Thethrough-hole 22 is arranged above the isolation trench 6 displaced fromthe active region L.

The bit lines BL are formed over the silicon oxide film 28. The bitlines BL are arranged above the isolation trenches 6 and extendstraightforwardly in the X-direction with the same width and space. Sucha bit line BL is formed of a W film and is electrically connected toeither one of the source and the drain of the memory cell selectingMISFET Qs (the n-type semiconductor region 9 shared by the two memorycell selecting MISFETs Qs) through the through-hole 22 formed in thesilicon oxide film 28 and the contact hole 19 formed in the underlyinginsulating films (the silicon oxide films 28, 18, 17, the SOG film 16and the gate oxide film 7). The space between each of the bit lines BLand the adjacent one is made as wide as possible so that the parasiticcapacitances formed between adjacent bit lines BL can be minimized.

By widening the spaces between the bit lines BL and reducing theparasitic capacitances, even if the memory cell size is scaled, it ispossible to increase the signal voltage required to read the charge(information) stored in the information storing capacitive elements C.In addition, by widening the spaces between the bit lines BL, it ispossible to sufficiently ensure the aperture margin of through-holes 48(to be described later) which are formed in the areas between the bitlines BL (through-holes for interconnecting the information storingcapacitive elements C and the contact holes 20). Accordingly, even ifthe memory cell size is scaled, it is possible to reliably prevent ashort circuit from occurring between the bit lines BL and thethrough-holes 48.

Furthermore, since the bit lines BL are formed of a metal (W), theirsheet resistance can be reduced to as low as 2Ω/, and it is possible toread/write information at high speeds. In addition, since the bit linesBL and interconnect lines 23 to 26 (to be described later) of theperipheral circuit can be formed in one step at the same time, it ispossible to simplify the process of manufacturing DRAMs. Since the bitlines BL are formed of a metal (W) having a high heat resistance andelectromigration resistance, it is possible to reliably preventdisconnection even if the width of the bit lines BL is scaled to a farsmaller size.

The first-layer interconnect lines 23 to 26 are formed over the siliconoxide film 28 of the peripheral circuit. These interconnect lines 23 to26 are formed of the same conducting material (W) as the bit lines BL,and are formed at the same time in the step of forming the bit lines BL,as will be described later. The interconnect lines 23 to 26 areelectrically connected to the MISFETs (the n-channel type MISFET Qn andthe p-channel type MISFET Qp) of the peripheral circuit through contactholes 30 to 34 formed in the silicon oxide films 28, 18 and 17 and theSOG film 16.

Plugs 35, each of which is formed of a conducting film in which a Tifilm, a TiN film and a W film are stacked in that order from the bottomlayer, are buried in the respective contact holes 30 to 34 whichinterconnect the MISFETs of the peripheral circuit and the interconnectlines 23 to 26. TiSi₂ (titanium silicide) layers 37, which are producedby the reaction between the Ti films which constitute part of the plugs35 and the semiconductor substrate 1 (Si), are respectively formed atthe bottoms of the contact holes (30 to 33) above the sources and thedrains of the MISFETs of the peripheral circuit (the n⁺-typesemiconductor regions 10 and the p⁺-type semiconductor regions 11),whereby the contact resistance between the plugs 35 and the sources andthe drains (the n⁺-type semiconductor regions 10 and the p⁺-typesemiconductor regions 11) is reduced.

A silicon oxide film 38 is formed over the bit lines BL and thefirst-layer interconnect lines 23 to 26, and a SOG film 39 is formedover the silicon oxide film 38. The surface of the SOG film 39 isflattened to be approximately equal in height over the entire area ofthe semiconductor substrate 1.

A silicon nitride film 44 is formed over the SOG film 39 of the memoryarray, and the information storing capacitive elements C are formedabove the silicon nitride film 44. Each of the information storingcapacitive elements C includes a lower electrode (storage electrode) 45,an upper electrode (plate electrode) 47, and a Ta₂O₅ (tantalum oxide)film 46 formed between the electrodes 45 and 47. The lower electrode 45is formed of a low-resistance polycrystalline silicon film doped with,for example, P (phosphorous), and the upper electrode 47 is formed of,for example, a TiN film.

The lower electrode 45 of the information storing capacitive element Cis formed in an elongate pattern extending straightforwardly in theX-direction as viewed in FIG. 4. The lower electrode 45 is electricallyconnected to the plug 21 in the contact hole 20 through a plug 49 buriedin the through-hole 48 which extends through the silicon nitride film44, the SOG film 39 and the underlying silicon oxide films 38 and 28,and is further electrically connected to either one of the source andthe drain (the n-type semiconductor regions 9) of the memory cellselecting MISFET Qs via the plug 21. The through-hole 48 which is formedbetween the lower electrode 45 and he contact hole 20 has a diameter(for example, 0.14 μm) smaller than the minimum process dimension inorder to reliably prevent a short circuit from occurring between the bitline BL or the underlying plug 35. The plug 49 buried in thethrough-hole 48 is formed of a low-resistance polycrystalline siliconfilm doped with P (phosphorous).

A silicon oxide film 50 having a large film thickness, which isapproximately equal in height to the lower electrode 45 of theinformation storing capacitive element C, is formed over the SOG film 39of the peripheral circuit. Since the silicon oxide film 50 of theperipheral circuit is formed with such a large film thickness, thesurface of an interlayer insulating film 56 which is formed above theinformation storing capacitive elements C is approximately equal inheight between the memory array and the peripheral circuit.

The interlayer insulating film 56 is formed above the informationstoring capacitive elements C, and second-layer interconnect lines 52and 53 are formed above the interlayer insulating film 56. Theinterlayer insulating film 56 is formed of a silicon oxide film, and thesecond-layer interconnect lines 52 and 53 are formed of a conductingfilm which is mainly made of Al (aluminum). The second-layerinterconnect line 53 formed in the peripheral circuit is electricallyconnected to the first-layer interconnect line 26 through a through-hole54 which is formed to extend through the underlying insulating films(the interlayer insulating film 56, the silicon oxide film 50, the SOGfilm 39 and the silicon oxide film 38). A plug 55 which is formed of,for example, a Ti film, a TiN film and a W film is buried in thethrough-hole 54.

A second-layer insulating film 63 is formed above the second-layerinterconnect lines 52 and 53, and third-layer interconnect lines 57, 58and 59 are formed over the second-layer insulating film 63. Thesecond-layer insulating film 63 is formed of an silicon oxide-basedinsulating film (for example, a three-layer insulating film formed of asilicon oxide film, an SOG film and a silicon oxide film), and thethird-layer interconnect lines 57, 58 and 59 are formed of a conductingfilm which is mainly made of Al (aluminum), similarly to thesecond-layer interconnect lines 52 and 53.

The third-layer interconnect line 58 is electrically connected to theupper electrode 47 of the information storing capacitive element Cthrough a through-hole 60 formed in the underlying interlayer insulatingfilm 63 and 56, and the third-layer interconnect line 59 is electricallyconnected to the second-layer interconnect line 53 through athrough-hole 61 formed in the underlying interlayer insulating film 63.Plugs 62 each of which is made of, for example, a Ti film, a TiN filmand a W film are buried in the respective through-holes 60 and 61.

One example of a method of manufacturing the DRAM which is constructedin the above-described manner will be described below in the order ofprocess steps with reference to FIGS. 5 to 38.

First of all, as shown in FIG. 5, the isolation trenches 6 are formed inthe isolation regions of the principal surface of the semiconductorsubstrate 1 made of p-type single-crystal silicon having a resistivityof approximately 10 Ωcm. The isolation trenches 6 are formed by etchingthe surface of the semiconductor substrate 1 to form trenchesapproximately 30-400 nm deep, then depositing the silicon oxide film 5over the semiconductor substrate 1 as well as on the interiors of therespective trenches by a CVD method, and subsequently polishing back ofthe silicon oxide film 5 by a chemical mechanical polishing (CMP)method.

Then, as shown in FIG. 6, the n-type semiconductor area 3 is formed byion-implanting an n-type impurity, for example, P (phosphorus), into thearea (memory array) of the semiconductor substrate 1 in which memorycells are to be formed. After that, the p-wells 2 are formed byion-implanting an p-type impurity, for example, B (boron), into aportion of the memory array and a portion of the peripheral circuit (anarea in which the n-channel type MISFET Qn is to be formed), and then-well 4 is formed by ion-implanting an n-type impurity, for example, P(phosphorus), into another portion of the peripheral circuit (an area inwhich the p-channel type MISFET Qp is to be formed).

Then, an impurity for adjusting the threshold voltages of the MISFETs,for example, BF₂ (boron fluoride), is ion-implanted into the p-wells 2and the n-well 4, and after the surfaces of the p-wells 2 and the n-well4 are cleaned by a HF (hydrofluoric acid)-based cleaning liquid, thesemiconductor substrate 1 is wet-etched to form a clean gate oxide film7 having a film thickness of approximately 7 nm over the surfaces of thep-wells 2 and the n-well 4.

Then, as shown in FIG. 7, the gate electrodes 8A (word lines WL) and thegate electrodes 8B and 8C are formed above the gate oxide film 7. Thegate electrodes 8A (word lines WL) and the gate electrodes 8B and 8C areformed by depositing an approximately-70-nm-thick polycrystallinesilicon film doped with an n-type impurity such as P (phosphorous) overthe semiconductor substrate 1 by a CVD method, depositing anapproximately-5-nm-thick WN (tungsten nitride) film and anapproximately-100-nm-thick W film over the polycrystalline silicon filmby a sputtering method, depositing an approximately-200-nm-thick siliconnitride film 12 over the W film by a CVD method, and patterning thesefilms by using a photoresist film as a mask. The WN film functions as abarrier layer which prevents the W film and the polycrystalline siliconfilm from reacting with each other to form a high-resistance silicidefilm at the interface between both films. The barrier layer may also usea WN-film high-melting-point metal film, for example, a TiN (titaniumnitride) film. The gate electrodes 8A (word lines WL) of the memory cellselecting MISFETs Qs are formed by using a phase shift technique and anexposure technique which uses, for example, a KrF excimer laser having awavelength of 248 nm as a light source.

Then, as shown in FIG. 8, an p-type impurity, for example, B (boron), ision-implanted into the n-well 4 to form p⁻-type semiconductor regions 15in the n-well 4 on both sides of the gate electrode 8C. In addition, ann-type impurity, for example, P (phosphorous), is ion-implanted into then-wells 2 to form the n⁻-type semiconductor regions 9 a in the n-well 2on both sides of each of the gate electrodes 8A, and to form n⁻-typesemiconductor regions 14 in the p-well 2 on both sides of the gateelectrode 8B. Through the above-described process steps, the memory cellselecting MISFETs Qs are approximately finished.

Then, as shown in FIG. 9, after an approximately-50-nm-thick siliconnitride film 13 is deposited over the semiconductor substrate 1 by a CVDmethod, the portion of the silicon nitride film 13 which is depositedover the memory array is covered with a photoresist film and the portionof the silicon nitride film 13 which is deposited over the peripheralcircuit is anisotropically etched away to form the sidewall spacers 13sover the sidewalls of the gate electrodes 8B and 8C of the peripheralcircuit. This etching is performed by using a gas which etches thesilicon nitride film 13 at a high selectivity, so as to minimize theamount of cutting of the silicon oxide film 5 buried in the isolationtrenches 6 as well as the gate oxide film 7. In addition, to minimizethe amount of cutting of the silicon nitride film 12 of the gateelectrodes 8B and 8C, the amount of overetching is reduced to thenecessary minimum amount.

Then, as shown in FIG. 10, a p-type impurity, for example, B (boron), ision-implanted into the n-well 4 of the peripheral circuit to form thep⁺-type semiconductor regions 11 (source and drain) of the p-channeltype MISFET Qp, and an n-type impurity, for example, As (arsenic), ision-implanted into the n-well 4 of the peripheral circuit to form then⁺-type semiconductor regions 10 a (source and drain) of the n-channeltype MISFET Qn. Through the above-described process steps, the p-channeltype MISFET Qp and the n-channel type MISFET Qn each having an LDDstructure are approximately finished.

Then, as shown in FIG. 11, an approximately-300-nm-thick SOG film 16 isformed over the semiconductor substrate 1 by spin coating, and after theSOG film 16 is baked in an oxygen atmosphere of approximately 400° C.which contains water vapor, the SOG film 16 is densified by anapproximately-one-minute heat treatment of 800° C. The SOG film 16 uses,for example, a polysilazane-based inorganic SOG.

The SOG film 16 is high in reflow capability and superior in gap fillingcapability for fine spaces compared to a glass flow film such as a BPSGfilm, and even if the SOG film 16 is buried in the spaces between thegate electrodes 8A (word lines WL) which are scaled down to theresolution limit of photolithography, no void is produced. In addition,since the SOG film 16 can develop a high reflow capability even if thehigh-temperature, long-time heat treatment required for BPSG film or thelike is not performed on the SOG film 16, it is possible to restrainthermal diffusion of impurities implanted in the sources and drains ofthe memory cell selecting MISFETs Qs or in the sources and drains of theMISFETs (the n-channel type MISFET Qn and the p-channel type MISFET Qp)of the peripheral circuit, thereby realizing shallower junctions.Moreover, since the metal (W film) which constitutes the gate electrodes8A (the word lines WL) and the gate electrodes 8B and 8C can berestrained from being oxidized during heat treatment, it is possible toenhance the performance of the memory cell selecting MISFETs Qs and theMISFETs of the peripheral circuit.

Then, as shown in FIG. 12, an approximately-600-nm-thick silicon oxidefilm 17 is deposited over the SOG film 16, and then, after the siliconoxide film 17 is polished by a CMP method to flatten its surface, anapproximately-100-nm-thick silicon oxide film 18 is deposited over thesilicon oxide film 17. The overlying silicon oxide film 18 is depositedto repair fine scratches which occur on the surface of the underlyingsilicon oxide film 17 when the silicon oxide film 17 is polished by aCMP method.

Then, as shown in FIG. 13, the silicon oxide films 18 and 17 above then⁻-type semiconductor regions 9 a (sources and drains) of the memorycell selecting MISFETs Qs are removed by dry etching which uses aphotoresist film 27 as a mask. This etching is performed by using a gaswhich etches the silicon oxide film 17 at a high selectivity, so as toprevent the removal of the silicon nitride film 13 which underlies thesilicon oxide film 17.

Then, as shown in FIG. 14, the silicon nitride film 13 above the n⁻-typesemiconductor regions (sources and drains) 9 a is removed by dry etchingwhich uses the photoresist film 27 as a mask, and then, the underlyingthin gate oxide film 7 is removed to form the contact hole 19 above oneof the n⁻-type semiconductor regions (sources and drains) 9 a and thecontact holes 20 above the other ones.

The etching of the silicon nitride film 13 is performed by using a gaswhich etches the silicon nitride film 13 at a high selectivity, so as tominimize the amount of cutting of the semiconductor substrate 1 as wellas the isolation trenches 6. This etching is performed under such acondition that the silicon nitride film 13 is anisotropically etchedaway, so as to leave the silicon nitride film 13 on the sidewalls of thegate electrodes 8A (word lines WL). Thus, the fine contact holes 19 and20 whose bottom diameters (diameters in the X-direction) are not greaterthan the resolution limit of lithography can be formed by self-alignmentwith respect to the spaces between the gate electrodes 8A (word linesWL).

Then, after the photoresist film 27 is removed, a hydrofluoricacid-based cleaning liquid (for example, a mixture of hydrofluoric acidand ammonium fluoride) is used to clean the surface of the semiconductorsubstrate 1 which is exposed at the bottom of each of the contact holes19 and 20, thereby removing drying etching residues, photoresistresidues and the like. At this time, the SOG film 16 exposed at thesidewalls of the contact holes 19 and 20 is exposed to the etchant, butsince the SOG film 16 which is densified at a high temperature ofapproximately 800° C. has a high resistance to the hydrofluoricacid-based cleaning liquid compared to non-densified SOG films, thesidewalls of the contact holes 19 and 20 are not undercut to a greatextent by this wet etching treatment. Thus, it is possible to reliablyprevent a short circuit from occurring between the plugs 21 to be buriedin the respective contact holes 19 and 20 in the next process step.

After the contact holes 19 and 20 are formed, an n-type semiconductorlayer may also be formed in the region of the p-well 2 which is deeperthan the sources and drains of the memory cell selecting MISFETs Qs, byion-implanting an n-type impurity (for example, phosphorus) into thep-well 2 through the contact holes 19 and 20. The n-type semiconductorlayer has the effect of relaxing electric fields which concentrate onthe edge portions of the sources and drains, and is capable ofdecreasing leakage current at the edge portions of the sources anddrains and improving the refresh characteristics.

Then, as shown in FIG. 15, the plugs 21 are formed in the respectivecontact holes 19 and 20. The plugs 21 are formed by depositing anapproximately-300-nm-thick polycrystalline silicon film doped with ann-type impurity (for example, As (arsenic)) over the silicon oxide film18 by a CVD method and polishing the polycrystalline silicon film by aCMP method to leave the polycrystalline silicon film in only the contactholes 19 and 20.

Then, after an approximately-200-nm-thick silicon oxide film 28 isdeposited over the silicon oxide film 18 by a CVD method, heat treatmentis performed in a nitrogen gas atmosphere at 800° C. for approximatelyone minute. Through this heat treatment, the n-type impurity in thepolycrystalline silicon film which constitutes the plugs 21 is diffusedfrom the bottoms of the contact holes 19 and 20 into the n⁻-typesemiconductor regions 9 a of the memory cell selecting MISFETs Qs,whereby the low-resistance n-type semiconductor regions (source anddrain) 9 are formed.

Then, as shown in FIG. 16, the through-hole 22 is formed by removing thesilicon oxide film 28 from the top of the contact hole 19 by dry etchingusing a photoresist film as a mask. This through-hole 22 is arrangedabove the isolation trench 6 displaced from the active region L.

Then, the silicon oxide films 28, 18 and 17, the SOG film 16 and thegate oxide film 7 of the peripheral circuit are removed by dry etchingusing a photoresist film as a mask, whereby the respective contact holes30 and 31 are formed above the p⁺-type semiconductor regions (source anddrain) 11 of the n-channel type MISFET Qn and the respective contactholes 32 and 33 are formed above the p⁺-type semiconductor regions(source and drain) 11 of the p-channel type MISFET Qp. At the same time,the contact hole 34 is formed above the gate electrode 8C of thep-channel type MISFET Qp and a contact hole (not shown) is formed abovethe gate electrode 8B of the n-channel type MISFET Qn.

As described above, by performing etching for forming the through-hole22 and etching for forming the contact holes 30 to 34 in separateprocess steps, it is possible to prevent the problem that the plug 21exposed at the bottom of the shallower through-hole 22 of the memoryarray is deeply cut when the deeper contact holes 30 to 34 of theperipheral circuit are being formed. Incidentally, the formation of thethrough-hole 22 and that of the contact holes 30 to 34 may also beperformed in reverse order to the above-described one.

Then, as shown in FIG. 17, an approximately-40-nm-thick Ti film 36 isdeposited over the silicon oxide film 28 as well as the interiors of thecontact holes 30 to 34 and the through-hole 22. The Ti film 36 isdeposited by using high-directivity sputtering such as collimationsputtering, so that a film thickness of approximately 100 nm or more canbe ensured even at the bottoms of the contact holes 30 to 34 havinglarge aspect ratios.

Then, heat treatment is performed in an Ar (argon) gas atmosphere at650° C. for approximately 30 seconds without exposing the Ti film 36 tothe atmosphere, and further heat treatment is performed in a nitrogengas atmosphere at 750° C. for approximately one minute. In this heattreatment, as shown in FIG. 18, the Ti film 36 and the Si substratereact with each other at the bottoms of the contact holes 30 to 34 andan approximately-10-nm-thick TiSi₂ layer 37 is formed over the surfacesof the n⁺-type semiconductor regions (source and drain) 10 of then-channel type MISFET Qn and over the surfaces of the p⁺-typesemiconductor regions (source and drain) 11 of the p-channel type MISFETQp. In the aforementioned heat treatment in the nitrogen gas atmosphere,the surface of the thin Ti film 36 which is deposited over the sidewallsof the contact holes 30 to 34 is nitrified and becomes a stable filmwhich does not easily react with Si.

During this time, the surface of the Ti film 36 over the silicon oxidefilm 28 is also nitrified, but the portion of the Ti film 36 other thanthe surface remains unreacted. The TiSi₂ layer 37 is formed over thesurface of the plug 21 at the bottom of the through-hole 22 by thereaction between the Ti film 36 and the polycrystalline silicon filmwhich constitutes the plug 21.

By forming the TiSi2 layers 37 at the bottoms of the contact holes 30 to34, it is possible to decrease the contact resistance to 1 kΩ or less ina portion in which the plugs 35 formed in the contact holes 30 to 33 arerespectively brought into contact with the sources and drains (then⁺-type semiconductor regions 10 and the p⁺-type semiconductor regions11) of the MISFETs of the peripheral circuit in the next process step.Accordingly, it is possible to realize high-speed operation ofperipheral circuits such as the sense amplifiers SA and the word driversWD. The silicide layer at the bottom of each of the contact holes 30 to34 may be made of high melting-point metal silicide other than TiSi₂,for example, CoSi₂ (cobalt silicide), TaSi₂ (tantalum silicide) or MoSi₂(molybdenum silicide).

Then, as shown in FIG. 19, an approximately-30-nm-thick TiN film 40 isdeposited over the Ti film 36 by a CVD method. The CVD method issuperior in step coverage to the sputtering method and can deposit theTiN film 40, which is approximately equal in film thickness to the TiNfilm 40 deposited over the flat portion of the Ti film 36, at thebottoms of the contact holes 30 to 34 having large aspect ratios. Then,a thick W film 41 approximately 300 nm thick is deposited over the TiNfilm 40 by a CVD method which uses tungsten hexafluoride (WF₆),hydrogen, and monosilane (SiH₄) as a source gas, thereby completelyfilling the interiors of the contact holes 30 to 34 and the through-hole22 with the W film 41.

Incidentally, if an unreacted Ti film 36 is removed with an etchantimmediately after the TiSi₂ layer 37 is formed, the etchant flows intothe interior of the contact hole 34 formed above the gate electrode 8Cof the p-channel type MISFET Qp and into the interior of a contact hole(not shown) formed above the gate electrode 8B of the n-channel typeMISFET Qn, so that the surfaces of the gate electrodes 8B and 8C (Wfilms) each having a poly-metal structure are etched. To prevent thisphenomenon, in the present embodiment, after the TiSi₂ layer 37 isformed at the bottoms of the contact holes 30 to 33, the TiN film 40 andthe W film 41 are deposited above the unreacted Ti film 36 which is lefton the silicon oxide film 28 and in the contact holes 30 to 34.

Then, as shown in FIG. 20, the plugs 35 each formed of the W film 41,the TiN film 40 and the Ti film 36 are formed in the respective contactholes 30 to 34 and the through-hole 22 by removing (polishing back) theW film 41, the TiN film 40 and the Ti film 36 formed above the siliconoxide film 28, using a CMP method. The plugs 35 may also be formed byremoving (polishing back) the W film 41, the TiN film 40 and the Ti film36 formed over the silicon oxide film 28, by dry etching. Incidentally,it is necessary to notice that if the removal of the Ti film 36 from thesilicon oxide film 28 is insufficient, interconnect lines (23 to 26) tobe formed over the silicon oxide film 28 in the next process step maypartly peel off the surface of the silicon oxide film 28 during a laterhigh-temperature treatment.

The plugs 35, which are mainly formed of the W film 41 which is a highmelting-point metal, have a low resistance and a high heat resistance.The TiN film 40 which is formed below the W film 41 functions as abarrier layer which prevents tungsten hexafluoride and Si from reactingwith each other to produce defects (encroachment or worm holes) when theW film 41 is deposited by a CVD method, and also as a barrier layerwhich prevents the W film 41 and the Si substrate from reacting witheach other (pagesilicidication reaction) in a later high-temperaturetreatment step. This barrier layer may also use a high-melting-pointmetal nitride other than TiN (for example, WN film).

The plugs 35 may be mainly formed of the TiN film 40 without the use ofthe W film 41. Specifically, the plugs 35 may be formed by burying athick TiN film 40 in each of the contact holes 30 to 34 and thethrough-hole 22. In this case, the plugs 35 are somewhat higher inresistance than those mainly formed of the W film 41, but the TiN film40 serves as an etching stopper when the bit lines BL and thefirst-layer interconnect lines 23 to 26 of the peripheral circuit are tobe formed by dry-etching a W film 42 deposited over the silicon oxidefilm 28 in the next process step, so that the misalignment marginbetween the interconnect lines 23 to 26 and the contact holes 30 to 34is remarkably improved and the degree of freedom of layout of theinterconnect lines 23 to 26 is greatly improved.

Then, the bit lines BL and the first-layer interconnect lines 23 to 26of the peripheral circuit are formed over the silicon oxide film 28 by amethod which will be described below.

First, as shown in FIG. 21, after polish residues are fully removed fromthe surface of the silicon oxide film 28 by wet cleaning, anapproximately-100-nm-thick W film 42 is deposited over the silicon oxidefilm 28 by a sputtering method. Then, as shown in FIG. 22, the bit linesBL and the first-layer interconnect lines 23 to 26 of the peripheralcircuit are formed by dry-etching the W film 42 by using a photoresistfilm 43 formed over the W film 42 as a mask. Incidentally, since the Wfilm 42 has a high optical reflectivity, the photoresist film 43 maycause halation during exposure and the dimensional accuracy of a pattern(width and space) may decrease. To prevent this phenomenon, after a thinanti-reflection film is deposited on the W film 42, the anti-reflectionfilm may be coated with the photoresist film 43. The anti-reflectionfilm may use an organic material or a metallic material of low opticalreflectivity (for example, TiN film).

The result of examination of the adhesion between silicon oxide film andseveral kinds of metal films deposited thereon will be described below.

TABLE 1 Sample Number Specifications Interfacial Status Remark 1W/TiN/Ti Occurrence of Peeling 2 W/TiN/TiNx Occurrence of Peeling x =10% 3 W/TiN/TiNx Occurrence of Peeling x = 15% 4 W/TiN/TiNx Occurrenceof Peeling x = 20% 5 W/TiN No Peeling 6 W No Peeling

Note 1) After 5-min 800° C. nitrogen annealing

Note 2) Plasma CVD-SiO₂ over the base and W

Table 1 shows the result obtained by depositing each of six kinds ofmetal films (Samples 1 to 6) over the surface of a silicon oxide filmdeposited by a plasma-CVD method, subjecting it to heat treatment in an800° C. nitrogen atmosphere for five minutes, and estimating theadhesion of the interface between the metal film and the surface of thesilicon oxide film. In each of the samples, the W film was depositedwith a film thickness of 300 nm by a sputtering method. The TiN film ofeach of Samples 1 to 5 was deposited with a film thickness of 50 nm by areactive sputtering method. The TiN_(x) films of Samples 2, 3 and 4 aredeposited to have different composition ratios (x), by a reactivesputtering method. Specifically, the composition ratios (x) were madedifferent by adjusting the oxygen partial pressure of a gaseous mixtureof Ar (argon) and nitrogen. The Ti film of Sample 1 was deposited with afilm thickness of 50 nm by a reactive sputtering method.

As shown in Table 1, peeling occurred at the interface of each ofSamples 1 to 4, but no peeling occurred in Samples 5 and 6. From thisfinding, it has been found out that film peeling occurs ifhigh-temperature heat treatment is performed with a Ti film or a Ticompound which contains an excess amount of Ti and a silicon oxide filmbeing in contact with each other at their interface. In this case, theenergy variation of thermochemical production energy for producingoxides is such that Si forms oxides more easily than W, and Ti formsoxides far more easily than Si. Therefore, it is presumed that suchinherent characteristic in each substance is the cause of theabove-described film peeling. If Ti is present at the interface not as asimple substance (Ti) but as a stable nitrogen compound (TiN), energywhich destroys the Ti—N coupling becomes necessary, and this isconsidered to be why no film peeling occurred in Sample 5.

Incidentally, in the through-hole 22 and the contact holes 30 to 34,their sidewalls remain in contact with a Ti film 22, but there is noproblem because the plugs 35 in the through-hole 22 and the contactholes 30 to 34 adhere to the underlying polycrystalline silicon plug 21or the semiconductor substrate or because the bit lines BL or theinterconnect lines 23 to 26 are present above the plugs 35.

In the above-described manufacturing method, the bit lines BL and theinterconnect lines 23 to 26 are formed by removing the W film 41, theTiN film 40 and the Ti film 36 deposited over the silicon oxide film 28,forming the plugs 35 in the contact holes 30 to 34 and the through-hole22, and patterning the W film 42 newly deposited over the silicon oxidefilm 28. Therefore, according to this method, the number ofmanufacturing process steps increases as compared with the case offorming the bit lines BL and the interconnect lines 23 to 26 bypatterning the W film 41, the TiN film 40 and the Ti film 36, but it ispossible to reliably prevent a failure in which the bit lines BL or theinterconnect lines 23 to 26 cause film peeling during high-temperatureheat treatment which is performed later when the information storingcapacitive element C is to be formed above the bit lines BL.

In addition, according to the above-described manufacturing method ofdepositing the W film 2 over the silicon oxide film 28 the for formingthe bit lines BL and the interconnect lines 23 to 26, after forming theplugs 35 in the contact holes 30 to 34, each having a large aspectratio, it is not necessary to take into account the burying of a filminto the through-hole 22 and the contact holes 30 to 34 when the W film42 is to be deposited, so that it is possible to deposit the W film 42with a small film thickness. Specifically, according to thismanufacturing method, since the film thickness of the bit lines BL canbe made small, it is possible to reduce the parasitic capacitancesformed between adjacent bit lines BL.

Furthermore, since the surface of the silicon oxide film 28 is polishedand flattened by a CMP method and the W film 42 having a large thicknessis deposited over the surface, it is possible to decrease the amount ofoveretching of the W film 42 during etching thereof, whereby it ispossible to prevent the problem of deeply cutting the plug 35 in thethrough-hole 22 having a diameter larger than the width of thephotoresist film 43.

The bit lines BL and the interconnect lines 23 to 26 may be formed witha W film deposited by a CVD method or a layer in which a W film and aTiN film are stacked. The bit lines BL and the interconnect lines 23 to26 may also be formed with another high melting-point metal (forexample, Mo film or Ta film) having good adhesion to a siliconoxide-based insulating film, a single-layer film of a nitride of suchhigh melting-point metal, or a film in which such single-layer films arestacked.

Then, as shown in FIG. 23, an approximately-100-nm-thick silicon oxidefilm 38 is deposited over the bit lines BL and the first-layerinterconnect lines 23 to 26, and after an approximately-250-nm-thick SOGfilm 39 is formed over the silicon oxide film 38 by spin coating, theSOG film 39 is baked in an oxygen atmosphere of approximately 400° C.which contains water vapor. Then, the SOG film 39 is densified by anapproximately-one-minute heat treatment of 800° C., whereby the surfaceof the SOG film 39 is flattened.

As described above, since the surface of the silicon oxide film 28 isflattened and the thin W film 42 is deposited over the surface to formthe bit lines BL and the first-layer interconnect lines 23 to 26, it ispossible to reduce the step height of a base portion which underlies theSOG film 39, whereby it is possible to form a flat layer over the bitlines BL and the interconnect lines 23 to 26, by using only a two-layerinsulating film (the silicon oxide film 38 and the SOG film 39).Specifically, it is possible to ensure sufficient flatness without theneed to deposit a silicon oxide film (17) over an SOG film (16) andpolish the surface of the silicon oxide film by a CMP method similarlyto the process step of flattening the tops of the gate electrodes 8A, 8Band 8C, whereby it is possible to reduce the number of process steps.

Incidentally, if the step height due to the bit lines BL and thefirst-layer interconnect lines 23 to 26 is small, it is possible to forma flat layer merely by thickly depositing a silicon oxide film 38without using the SOG film 39. On the other hand, if the difference indensity between the bit lines BL and the interconnect lines 23 to 26 islarge and no sufficient flatness can be obtained with only the SOG film39, the surface of the SOG film 39 may be polished by a CMP method and asilicon oxide film for repairing fine scratches on the surface of theSOG film 39 may also be deposited over the SOG film 39. If thetemperature required to densify the SOG film 39 cannot be made veryhigh, a silicon oxide film may also be deposited over the SOG film 39 tocompensate for a decrease in the humidity resistance thereof.

Then, as shown in FIG. 24, through-holes 71 are formed above the contactholes 20 by depositing an approximately-200-nm-thick polycrystallinesilicon film 70 over the SOG film 39 by a CVD method, and dry-etchingthe polycrystalline silicon film 70 by using a photoresist film as amask. These through-holes 71 are formed to be approximately equal indiameter to their minimum process dimensions.

Then, as shown in FIG. 25, sidewall spacers 72 each made of apolycrystalline silicon film are respectively formed over the sidewallsof the through-holes 71. The sidewall spacers 72 are formed bydepositing a second polycrystalline silicon film which is as thin asapproximately 60 nm (not shown) over the polycrystalline silicon film 70as well as on the interiors of the through-holes 71, and then etchingback the polycrystalline silicon film to leave it on the sidewalls ofthe through-holes 71. By forming the sidewall spacers 72, the innerdiameter of each of the through-holes 71 becomes smaller than theminimum process dimension.

Then, as shown in FIG. 26, the through-holes 48 which reach therespective contact holes 20 through the area between a bit line BL andan adjacent bit line BL are formed by dry-etching the insulating films(the SOG film 39 and the silicon oxide films 38 and 28) which underliethe through-holes 71, using the polycrystalline silicon film 70 and thesidewall spacers 72 as a mask.

Since the through-holes 48 are formed by using as a mask the sidewallspacers 72 on the sidewalls of the through-holes 71 each having an innerdiameter smaller than the minimum process dimension, the inner diametersof the through-holes 48 are smaller than their minimum processdimensions. Accordingly, it is possible to fully ensure the alignmentmargin between the space areas between the bit line BL and thethrough-holes 48, whereby it is possible to reliably prevent a shortcircuit from occurring between the plugs 49 to be buried in thethrough-holes 48 in the next process step and the bit line BL or theunderlying plug 35.

Then, as shown in FIG. 27, an approximately-200-nm-thick polycrystallinesilicon film (not shown) doped with an n-type impurity such as P(phosphorous) is deposited over the polycrystalline silicon film 70 aswell as the interiors of the through-holes 48 by a CVD method, and thepolycrystalline silicon film is etched back together with thepolycrystalline silicon film 70 and the sidewall spacers 72 to form theplugs 49 made of the polycrystalline silicon film in the respectivethrough-holes 48.

Then, as shown in FIG. 28, an approximately-200-nm-thick silicon nitridefilm 44 is deposited over the SOG film 39 by a CVD method, and theportion of the silicon nitride film 44 which overlies the peripheralcircuit is removed by dry etching using a photoresist film as a mask.The silicon nitride film 44 which is left over the memory array is usedas an etching stopper when an silicon oxide film is being etched in thestep of forming the lower electrodes 45 of the information storingcapacitive elements C to be described later.

Then, as shown in FIG. 29, the silicon oxide film 50 is deposited overthe silicon nitride film 44 by a CVD method, and the silicon oxide film50 and the underlying silicon nitride film 44 are dry-etched using aphotoresist film as a mask, thereby forming recesses 73 above therespective through-holes 48. Since the respective lower electrodes 45 ofthe information storing capacitive elements C are formed along the innerwalls of the recesses 73, it is necessary to deposit the silicon oxidefilm 50 with a large film thickness (for example, approximately 1.3 μme)so that the surface area of each of the lower electrodes 45 can beincreased to increase the charge storage quantity.

Then, as shown in FIG. 30, an approximately-60-nm-thick polycrystallinesilicon film 45A doped with an n-type impurity such as P (phosphorous)is deposited over the silicon oxide film 50 as on well as the interiorsof the recesses 73 by a CVD method. This polycrystalline silicon film45A is used as a lower electrode material for the information storingcapacitive elements C.

Then, as shown in FIG. 31, an approximately-300-nm-thick SOG film 74 isformed over the polycrystalline silicon film 45A as on well as theinteriors of the recesses 73 by spin coating, and after the SOG film 74is baked by a heat treatment of approximately 400° C., the SOG film 74outside the recesses 73 is removed by an etch-back process.

Then, as shown in FIG. 32, the portion of the polycrystalline siliconfilm 45A which overlies the peripheral circuit is covered with aphotoresist film 75 and the portion of the polycrystalline silicon film45A which overlies the silicon oxide film 50 of the memory array isremoved by an etch-back process (anisotropic etching), whereby the lowerelectrodes 45 are formed along the inner walls of the respectiverecesses 73. The lower electrodes 45 may also be formed of a conductingfilm other than the polycrystalline silicon film 45A. It is desirablethat the conducting film for the lower electrodes 45A be formed of aconducting material which has a heat resistance and oxidation resistancewhich are not so weak as to degrade during high-temperature heattreatment of a capacitive insulating film to be performed in the nextprocess step, for example, a high melting-point metal such as W or Ru(ruthenium) or a conducting metal oxide such as RuO (ruthenium oxide) orIrO (iridium oxide).

Then, as shown in FIG. 33, after the silicon oxide film 50 which is leftbetween the recesses 73 and the SOG films 74 which are left in therespective recesses 73 are simultaneously removed by a hydrofluoricacid-based etchant, the photoresist film 75 is removed. Then, thepolycrystalline silicon film 45A which overlies the peripheral circuitis removed by dry etching using as a mask a photoresist film whichcovers the memory array, thereby finishing the lower electrodes 45 eachhaving a cylindrical shape. Since the silicon nitride film 44 is formedat the bottom of the silicon oxide film 50 between the recesses 73, theunderlying SOG film 39 is not etched during wet etching of the siliconoxide film 50. At this time, since the surface of the peripheral circuitis covered with the polycrystalline silicon film 45A, the underlyingthick silicon oxide film 50 is not etched.

By leaving the thick silicon oxide film 50 over the peripheral circuit,the interlayer insulating films 56 and 63 to be formed above theinformation storing capacitive elements C in a later process step aremade approximately equal in height between the memory array and theperipheral circuit. Accordingly, it is possible to facilitate formationof the second-layer interconnect lines 52 and 53 above the interlayerinsulating film 56, formation of the third-layer interconnect lines 57and 58 above the second-layer insulating film 63, and formation of thethrough-holes 60 and 61 which interconnect the second- and third-layerinterconnect lines.

Then, after a thin nitride film (not shown) is formed over the surfaceof each of the lower electrodes 45 by performing heat treatment at 300°C. for approximately three minutes in an ammonium atmosphere, a thinTa₂O₅ (tantalum oxide) film 46 of approximately 14 nm in thickness isdeposited over the lower electrodes 45 as shown in FIG. 34. The nitridefilm over the surfaces of the lower electrode 45 is formed to prevent apolycrystalline silicon film (45A) which constitutes the lowerelectrodes 45 from being oxidized by heat treatment to be nextperformed. The Ta₂O₅ film 46 is deposited by a CVD method which uses,for example, a pentaethoxy tantalum (Ta(OC₂H₅) as a source gas. TheTa₂O₅ film 46 formed by the CVD method, which is superior in stepcoverage, is deposited with an approximately uniform thickness over theentire surfaces of the lower electrodes 45 each having athree-dimensional cylindrical shape.

Then, the Ta₂O₅ film 46 is heat-treated in an oxidizing atmosphere at800° C. for approximately three minutes. By performing thishigh-temperature heat treatment, the crystal defects produced in theTa₂O₅ film 46 are repaired to provide a crystallized good-quality Ta₂O₅film 46. Thus, leakage current from the information storing capacitiveelements C can be reduced, whereby DRAMs having improved refreshcharacteristics can be manufactured.

In addition, since each of the lower electrodes 45 of the informationstoring capacitive elements C is formed in a three-dimensionalcylindrical shape which is increased in its surface area and thecapacitive insulating film is formed of the Ta₂O₅ film 46 having adielectric constant of approximately 20-25, it is possible to ensure acharge storage quantity sufficient to hold information even if thememory call is scaled to a far smaller size.

In addition, since the underlying bit lines BL and the first-layerinterconnect lines 23 to 26 which are formed prior to the deposition ofthe Ta₂O₅ film 46 are formed of a W film having good adhesion to asilicon oxide-based insulating film, it is possible to reliably preventa failure in which the bit lines BL and the interconnect lines 23 to 26cause film peeling due to the high-temperature heat treatment of theTa₂O₅ film 46.

In addition, since the bit lines BL are formed of a W film having a highheat resistance, it is possible to reliably prevent a failure in whichthe bit lines BL each of which is formed to have a small width notgreater than the minimum process dimension are degraded or disconnecteddue to the high-temperature heat treatment of the Ta₂O₅ film 46.Furthermore, since the plugs 35 in the contact holes 30 to 35 whichconnect the MISFETs of the peripheral circuit and the first-layerinterconnect lines 23 to 26 are formed of a highly heat-resistantconducting material (W film/TiN film/Ti film), it is possible to preventthe problem that leakage current from a source or drain increases orcontact resistance increases due to the high-temperature heat treatmentof the Ta₂O₅ film 46.

The capacitive insulating film of the information storing capacitiveelements C may be formed of a high dielectric (ferro-dielectric) filmmade of a metal oxide such as BST, STO, BaTiO₃ (barium titanate), PbTiO₃(lead titanate), PZT (PbZr_(X)Ti_(1−X)O₃), PLT (PbLa_(X)Ti_(1−X)O₃) orPLZT. These high dielectric (ferro-dielectric) films have a commonnature which needs high-temperature heat treatment of at least 750° C.or more after they are formed, so that high-quality film having lesscrystal defects can be obtained. Accordingly, even if these highdielectric (ferro-dielectric) films are used, it is possible to obtainan effect similar to the above-described one.

Then, as shown in FIG. 35, after a TiN film is deposited over the Ta₂O₅film 46 by using a CVD method and a sputtering method, the TiN film andthe Ta₂O₅ film 46 are patterned by dry etching using a photoresist filmas a mask, thereby finishing the information storing capacitive elementsC each of which is formed of the upper electrode 47 made of the TiNfilm, a capacitive insulating film made of the Ta₂O₅ film 46, and thelower electrode 45 made of a polycrystalline silicon film (45A). Throughthe above-described process steps, the memory cell is finished whichincludes the memory cell selecting MISFETs Qs and the informationstoring capacitive elements C connected in series with the MISFETs Qs.The upper electrodes 47 of the information storing capacitive elements Cmay also be formed of a conducting film other than the TiN film, forexample, a W film.

Then, as shown in FIG. 36, after the interlayer insulating film 56 isformed above the information storing capacitive elements C, thethrough-hole 54 is formed above the first-layer interconnect line 26 byetching the interlayer insulating film 56, the silicon oxide film 50,the SOG film 39 and the silicon oxide film 38 of the peripheral circuitusing a photoresist film as a mask. The interlayer insulating film 56 isformed of, for example, an approximately-600-nm-thick silicon oxide filmdeposited by a CVD method.

Then, as shown in FIG. 37, after the plug 55 is formed in thethrough-hole 54, the second-layer interconnect lines 52 and 53 areformed above the interlayer insulating film 56. The plug 55 is formed bydepositing, for example, a Ti film on the interlayer insulating film 56,depositing a TiN film and a W film over the Ti film by a CVD method, andetching back (dry-etching) these films to leave them in only thethrough-hole 54. The second-layer interconnect lines 52 and 53 areformed by depositing an approximately-50-nm-thick Ti film, anapproximately-500-nm-thick Al (aluminum) film, anapproximately-50-nm-thick Ti film and an approximately-50-nm-thick TiNfilm over the interlayer insulating film 56 in that order by a CVDmethod, and patterning these films by dry etching using a photoresistfilm as a mask.

Since a process step which is accompanied by high-temperature heattreatment is not needed after the capacitive insulating film for theinformation storing capacitive elements C is formed, a conductingmaterial mainly made of Al which is inferior in heat resistance but lowin electrical resistance as compared with a high melting-point metal ora nitride thereof can be used as the material of the second-layerinterconnect lines 52 and 53 which are formed above the interlayerinsulating film 56. In addition, since no process step accompanied byhigh-temperature heat treatment is needed and the problem of filmpeeling does not occur, when the second-layer interconnect lines 52 and53 are to be formed above the interlayer insulating film 56 formed ofsilicon oxide, a Ti film can be used as a barrier metal at theinterfacial portion between each of the second-layer interconnect lines52 and 53 and the interlayer insulating film 56 to be brought intocontact with each of them.

Then, as shown in FIG. 38, after the second-layer insulating film 63 isformed above the second-layer interconnect lines 52 and 53, the portionsof the interlayer insulating films 63 and 56 which overlie theinformation storing capacitive elements C are etched to form thethrough-hole 60, and the portion of the interlayer insulating film 63which overlies the second-layer interconnect line 53 of the peripheralcircuit is etched to form the through-hole 61. The second-layerinsulating film 63 is formed of an approximately-300-nm-thick siliconoxide film deposited by, for example, a CVD method, anapproximately-400-nm-thick silicon oxide film formed over the siliconoxide film by spin coating, and an approximately-300-nm-thick siliconoxide film deposited over the approximately-400-nm-thick silicon oxidefilm by a CVD method. The baking of the SOG film which constitutes partof the second-layer insulating film 63 is performed at a temperature ofapproximately 400° C. to prevent degradation of the second-layerinterconnect lines 52 and 53 mainly made of Al and degradation of thecapacitive insulating film of the information storing capacitiveelements C.

After that, the plugs 62 are formed in the respective through-holes 60and 61 and the third-layer interconnect lines 57, 58 and 59 are thenformed above the interlayer insulating film, whereby the DRAM shown inFIG. 3 is nearly finished. The plugs 62 are formed of, for example, aconducting material (W film/TiN film/Ti film) identical to that of theplug 55, and the third-layer interconnect lines 57, 58 and 59 are formedof, for example, a conducting material (TiN film/Ti film/Al film/Tifilm) identical to that of the second-layer interconnect lines 52 and53. Incidentally, a dense insulating film having high waterproofproperties (for example, a two-layer insulating film made of a siliconoxide film and a silicon nitride film which are deposited by aplasma-CVD method) is deposited over the third-layer interconnect lines57, 58 and 59, but the illustration of such insulating film is omittedfor clarity.

Although the invention made by the present inventors has beenspecifically described with reference to an embodiment of the presentinvention, the present invention is not limited to the above-describedembodiment and various modifications can of course be made withoutdeparting from the spirit and scope of the present invention.

The present invention can also be applied to a semiconductor integratedcircuit device or the like in which a DRAM, a logic LSI and a flashmemory are arranged on a single semiconductor chip.

Effects which can be obtained from representative features of thepresent invention disclosed herein will be described in brief below.

According to the present invention, in a DRAM having acapacitor-over-bitline structure in which the capacitive insulating filmof information storing capacitive elements is formed of a highdielectric material, the portions of bit lines and interconnect lines ofa peripheral circuit which are in contact with at least an underlyingsilicon oxide film are formed of a high melting-point metal film otherthan titanium or cobalt, the bit lines and the interconnect lines beingarranged below the information storing capacitive elements, whereby theadhesion between the bit lines and the interconnect lines of theperipheral circuit and the silicon oxide film is improved and it ispossible to reliably prevent a failure in which peeling occurs at theinterface between the bit lines or the interconnect lines of theperipheral circuit and the silicon oxide film during high-temperatureheat treatment to be performed when the capacitive insulating film isbeing formed. Accordingly, it is possible to improve the reliability andthe manufacture yield of 256-Mbit large-capacity DRAMs andlater-generation DRAMs.

Incidentally, Japanese Patent Laid-Open No. 92794/1997 has beendiscovered through a search for a known example relative to “plugelectrode made of Ti/TiN/W” which is one constituent element of thepresent invention.

Although “plug electrodes made of Ti/TiN/W” are described in theabove-identified specification, bit lines and interconnect lines for aperipheral circuit all of which are formed in the same layer are made ofTi/TiN/W. Accordingly, peeling occurs at the interface between the bitlines and an underlying oxide film.

It is apparent, therefore, that Japanese Patent Laid-Open No. 92794/1997does not at all take into account the problem of peeling and utterlydiffers from the present invention.

What is claimed is:
 1. A semiconductor integrated circuit device inwhich an interconnect line which extends with at least a portion of saidinterconnect line being in contact with a silicon oxide-based firstinsulating film is formed over said first insulating film which isformed over a principal surface of a semiconductor substrate, and acapacitive element having a capacitive insulating film at least aportion of which is formed of a high dielectric film is formed over asecond insulating film formed over said interconnect line, wherein aportion of a conducting film which constitutes said interconnect line,which portion is in contact with said first insulating film over saidfirst insulating film, is formed of a high melting-point metal excludingtitanium or a nitride of a high melting-point metal.
 2. A semiconductorintegrated circuit device comprising a DRAM in which a memory cellselecting MISFET provided with a gate electrode formed integrally with aword line is formed in a first area over a principal surface of asemiconductor substrate, a bit line is formed over a silicon oxide-basedfirst insulating film which covers said memory cell selecting MISFET,said bit line being electrically connected to either one of a source anda drain of said memory cell selecting MISFET and extending in contactwith said first insulating film, and an information storing capacitiveelement is formed over a second insulating film formed over said bitline, said information storing capacitive element being electricallyconnected to the other of said source and drain of said memory cellselecting MISFET and having a capacitive insulating film at least aportion of which is formed of a high dielectric film, wherein a portionof a conducting film which constitutes said bit line, which portion isin contact with said first insulating film over said first insulatingfilm, is formed of a high melting-point metal excluding titanium or anitride of a high melting-point metal.
 3. A semiconductor integratedcircuit device according to claim 2, wherein said high dielectric filmis a tantalum oxide film which is subjected to heat treatment forcrystallization.
 4. A semiconductor integrated circuit device accordingto claim 2, wherein a conducting film which constitutes a gate electrodeof said memory cell selecting MISFET is at least partly formed of ametal film.
 5. A semiconductor integrated circuit device according toclaim 2, wherein a MISFET of a peripheral circuit of said DRAM is formedin a second area over the principal area of said semiconductorsubstrate, a first-layer interconnect line is formed over said siliconoxide-based first insulating film which covers said MISFET of saidperipheral circuit, said first-layer interconnect line beingelectrically connected to any one of a gate electrode, a source and adrain of said MISFET of said peripheral circuit and extending in contactwith said first insulating film, wherein a portion of a conducting filmwhich constitutes said first-layer interconnect line, which portion isin contact with said first insulating film over said first insulatingfilm, is formed of a high melting-point metal excluding titanium or anitride of a high melting-point metal.
 6. A semiconductor integratedcircuit device according to claim 5, wherein a titanium silicide layeris formed at a bottom of a contact hole which is opened in said firstinsulating film and electrically connects said first-layer interconnectline and said source or drain of said MISFET of said peripheral circuit.7. A semiconductor integrated circuit device according to claim 5,wherein each of said conducting films which respectively constitute saidbit line and said first-layer interconnect line is a tungsten film.
 8. Asemiconductor integrated circuit device according to claim 2, whereinsaid first-layer interconnect line is electrically connected to saidsource or drain of said MISFET of said peripheral circuit via a plugwhich is formed in said contact hole and is formed of a stacked filmmade of a titanium film and a barrier metal film or a stacked film madeof a titanium film, a barrier metal film and a tungsten film.
 9. Asemiconductor integrated circuit device according to claim 5, whereinsaid gate electrode of said MISFET of said peripheral circuit is formedof a metal film.
 10. A semiconductor integrated circuit device accordingto claim 5, wherein said first insulating film is a spin-on-glass filmor a silicon oxide film deposited by a CVD method.
 11. A semiconductorintegrated circuit device according to claim 5, wherein a second-layerinterconnect line which is electrically connected to said firstinsulating film is formed over a silicon oxide-based third insulatingfilm formed over said information storing capacitive element, and aportion of a conducting film which constitutes said second-layerinterconnect line is a titanium film, said portion being in contact withsaid first insulating film.
 12. A method of manufacturing asemiconductor integrated circuit device, comprising the steps of: (a)forming a silicon oxide-based first insulating film over a principalsurface of a semiconductor substrate and then depositing a conductingfilm a portion of which is in contact with said first insulating film,over said first insulating film, said portion being made of a highmelting-point metal excluding titanium or a nitride of a highmelting-point metal including titanium; (b) patterning said conductingfilm to form an interconnect line which extends with at least a portionof said interconnect line being in contact with said first insulatingfilm, and then forming a second insulating film over said interconnectline; and (c) forming a capacitive element made of a first electrode, adielectric film and a second electrode, over said second insulatingfilm, said capacitive-element forming step including heat treatment forimproving a film quality of said dielectric film.
 13. A method ofmanufacturing a semiconductor integrated circuit device, comprising thesteps of: (a) forming a memory cell selecting MISFET which constitutes amemory cell of a DRAM, in a first area over a principal surface of asemiconductor substrate, and forming a MISFET which constitutes aperipheral circuit of said DRAM, in a second area over said principalsurface of said semiconductor substrate; (b) forming a siliconoxide-based first insulating film over each of said memory cellselecting MISFET and said MISFET of said peripheral circuit; (c) forminga first contact hole in said first insulating film over at least one ofa source and a drain of said memory cell selecting MISFET, formingsecond contact holes in said first insulating film over said respectivesource and drain of said MISFET of said peripheral circuit, and forminga third contact hole in said first insulating film over a gate electrodeof said MISFET of said peripheral circuit; (d) depositing a titaniumfilm over said first insulating film as well as interiors of saidrespective second and third contact holes, and forming titanium silicidelayers over surfaces of a source and a drain of said MISFET of saidperipheral circuit which are respectively exposed at bottoms of saidsecond contact holes, by heat-treating said semiconductor substrate; (e)depositing a barrier metal film or a stacked film made of said barriermetal and a high melting-point metal film excluding titanium over saidtitanium film as well as interiors of said second and third contactholes and then forming plugs in said respective second and third contactholes by removing said barrier metal film or said stacked film over saidfirst insulating film together with said titanium film; (f) depositing aconducting film over said first insulating film, at least a portion ofsaid conducting film which is in contact with said first insulating filmbeing made of a high melting-point metal excluding titanium or a nitrideof a high melting-point metal; (g) patterning said conducting film toform a bit line to be electrically connected to one of said source andsaid drain of said memory cell selecting MISFET through said firstcontact hole, and forming a first-layer interconnect line of saidperipheral circuit to be electrically connected to said MISFET of saidperipheral circuit through said second contact holes or said thirdcontact hole; and (h) forming an information storing capacitive elementmade of a first electrode, a high dielectric film and a secondelectrode, over said second insulating film, said capacitive-elementforming step including heat treatment for improving a film quality ofsaid dielectric film.
 14. A method of manufacturing a semiconductorintegrated circuit device according to claim 13, wherein a conductingfilm which constitutes a gate electrode of said memory cell selectingMISFET and a gate electrode of said MISFET of said peripheral circuit isa stacked film made of a low-resistance polycrystalline silicon filmdoped with an impurity, a barrier metal film and a tungsten film.
 15. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 13, wherein said bit line and said first-layerinterconnect line of said peripheral circuit are made of a tungstenfilm.
 16. A method of manufacturing a semiconductor integrated circuitdevice according to claim 13, wherein said dielectric film is made of ametal oxide.
 17. A method of manufacturing a semiconductor integratedcircuit device according to claim 16, wherein said metal oxide istantalum oxide.
 18. A method of manufacturing a semiconductor integratedcircuit device according to claim 13, wherein heat treatment temperaturefor improving the film quality of said dielectric film is 750° C. ormore.
 19. A method of manufacturing a semiconductor integrated circuitdevice, comprising the steps of: (a) forming a memory cell selectingMISFET which constitutes a memory cell of a DRAM, in a first area over aprincipal surface of a semiconductor substrate, and forming a MISFETwhich constitutes a peripheral circuit of said DRAM, in a second areaover said principal surface of said semiconductor substrate; (b) forminga silicon oxide-based first insulating film over each of said memorycell selecting MISFET and said MISFET of said peripheral circuit; (c)forming a first contact hole in said first insulating film over at leastone of a source and a drain of said memory cell selecting MISFET,forming second contact holes in said first insulating film over saidrespective source and drain of said MISFET of said peripheral circuit,and forming a third contact hole in said first insulating film over agate electrode of said MISFET of said peripheral circuit; (d) depositinga cobalt film over said first insulating film as well as interiors ofsaid respective second and third contact holes, and forming cobaltsilicide layers over surfaces of a source and a drain of said MISFET ofsaid peripheral circuit which are respectively exposed at bottoms ofsaid second contact holes, by heat-treating said semiconductorsubstrate; (e) depositing a barrier metal film or a stacked film made ofsaid barrier metal and a high melting-point metal film excluding cobaltover said cobalt film as well as interiors of said second and thirdcontact holes and then forming plugs in said respective second and thirdcontact holes by removing said barrier metal film or said stacked filmover said first insulating film together with said cobalt film; (f)depositing a conducting film over said first insulating film, at least aportion of said conducting film which is in contact with said firstinsulating film being made of a high melting-point metal excludingcobalt or a nitride of a high melting-point metal; (g) patterning saidconducting film to form a bit line to be electrically connected to oneof said source and said drain of said memory cell selecting MISFETthrough said first contact hole, and forming a first-layer interconnectline of said peripheral circuit to be electrically connected to saidMISFET of said peripheral circuit through said second contact holes orsaid third contact hole; and (h) forming an information storingcapacitive element made of a first electrode, a high dielectric film anda second electrode, over said second insulating film, saidcapacitive-element forming step including heat treatment for improving afilm quality of said dielectric film.